1. Field of the Invention
The present invention relates to a heterojunction bipolar transistor and a method of manufacturing the same, and more particularly, it relates to a heterojunction bipolar transistor and a method of manufacturing the same, which can improve transistor performance and precise element size.
2. Description of the Prior Art
FIG. 6 is a sectional view showing an example of a conventional heterojunction bipolar transistor, which is manufactured by a method described in IEEE Electron Device Letters, Vol. EDL-5 (1984), p. 310.
This heterojunction bipolar transistor is formed by a semi-insulative substrate 1 which is provided thereon with a subcollector layer 3 in a region enclosed by semi-insulation regions 2 for inter-element isolation. Semi-insulation layers 4 are provided on the subcollector layer 3 to enclose a collector layer 5. An internal base layer 6 is formed on the collector layer 5 and external base layers 7 are formed on the semi-insulation layers 4 respectively. An emitter layer 8 and a cap layer 9 are formed on the internal base layer 6. Base electrodes 10 are formed on the external base layers 7, while an emitter electrode 11 is formed on the cap layer 9 and a collector electrode 12 is formed on the subcollector layer 3 respectively. Semi-insulation regions 13 for inter-electrode isolation are formed between the base electrodes 10 and the emitter electrode 11.
Such a heterojunction bipolar transistor is generally manufactured in the following manner:
First, a subcollector layer 3, a collector layer 5, an internal base layer 6, an emitter layer 8 and a cap layer 9 are sequentially epitaxially grown on the semi-insulative substrate 1.
Then, photoresist patterns for forming the external base layers 7 through photolithography or the like are formed on the cap layer 9 to ion-implant, e.g., beryllium atoms by utilizing the photoresist patterns as masks, thereby to form the external base layers 7. Further, oxygen atoms are ion-implanted through the said photoresist patterns into regions deeper than the external base layers 7, to form the semi-insulation layers 4 directly under the external base layers 7.
Thereafter the ion-implanted regions are annealed, i.e., the ion-implanted impurities are activated through heat treatment. Then the base electrodes 10 are formed on the external base layers 7 and the emitter electrode 11 is formed on the cap layer 9 to be subjected to alloying processing respectively. In order to form the collector electrode 12, after a corresponding part with the collector electrode 12 is removed by selective etching to reach the subcollector layer 3, the collector electrode 12 are formed.
Finally, boron atoms, for example, are ion-implanted to form the semi-insulation regions 13 for inter-electrode isolation and the semi-insulation regions 2 for inter-element isolation.
However, such a conventional method of manufacturing the heterojunction bipolar transistor has the following disadvantages: Ion implantation and annealing must be performed in order to form the external base layers 7 and the semi-insulation layers 4 respectively, whereby crystal structure of the ion-implanted regions is broken and the impurities are diffused by the annealing after ion implantation, to lower the transistor performance. Further, the element size cannot be precisioned since ion implantation of the extermal base layers 7 and formation of the emitter and base electrodes 11 and 10 are not performed in a self-alignment manner.